1. Field of the Invention
The present invention is concerned with a signal processor computing arrangement, and with a method of cyclically operating said computing arrangement for separately summing up two series of products with overlapping sets of operands.
In many signal processor applications such as computation of digital filter output values, a sequence of products of variable input values and given coefficients has to be accumulated for each such output value. While the set of coefficients may remain constant, the set of input values is shifted for subsequent output values, i.e., the leading input value is cancelled and a new trailing input value is added. Thus, for subsequent output values, overlapping sets of operands are used.
Microprocessors are particularly useful for signal processing applications because they can be incorporated in respective equipment.
A general description of such microprocessors was given in the paper "Microprocessors" by H. M. D. Toong, published in Scientific American, September 1977, pp. 146-161. Above-mentioned operations can be performed on these general purpose microprocessors which are also suited for all other kinds of data processing operations.
2. Description of Prior Art
Microprocessors which are specifically suited for signal processing applications were recently disclosed in two publications.
One of them entitled "V-MOS Chip Joins Microprocessor to Handle Signals in Real Time" by R. W. Blasco, appeared in Electronics on Aug. 30, 1979, pp. 131-138. The described processor provides an adder/subtractor unit and an additional multiplier which allow sequential multiplication and adding/subtracting operations. The required multiplication unit, however, is a very high-speed multiplier because it must provide a product of two operands within one cycle. Operands for subsequent computations have to be fetched from memory each time they are used again.
Another publication "Packaging a Signal Processor Onto a Single Digital Board" by L. Schirm, Electronics, Dec. 20, 1979 describes a processor using specific multiplier-accumulator units. A parallel arrangement of several such units allows the parallel generation of subsequent output values, using each input value in several computations. Several accumulating, i.e., adding/subtracting units and several high-speed multipliers have to be dedicated to this arrangement. Furthermore, this equipment is not available for other necessary general processing operations.